1. Field of the Invention
The present invention relates to a semiconductor device including MIS transistors having different channel profiles and a method of fabricating the same.
2. Description of the Prior Art
In association with increase in integration, functionality, and speed of a semiconductor integrated circuit device in recent years, the cell area of an SRAM which is to be integrated has been reduced, and the size of a MIS transistor constituting the SRAM has been greatly reduced. However, there is a problem that reducing in size of the MIS transistor increases a random variation of characteristics caused by channel impurities and realizes no operating margin as the SRAM, which leads to an inoperative condition.
For reducing random components of the variation, a so-called retrograde channel structure is effective (see Japanese Laid-Open Patent Publication No. 5-335564). The retrograde channel structure has such an impurity profile of a channel region that the impurity concentration is low at an interface between a gate oxide film and a semiconductor substrate and an impurity concentration peak is located in the interior of the substrate.
A conventional method of fabricating a MIS transistor having a retrograde channel structure will be described with reference to cross sections illustrating steps in FIG. 10A through FIG. 10C.
As described with reference to FIG. 10A, on a p-type semiconductor substrate 101, device isolation regions 102 are formed. Then, a gate oxide film 103 and a gate electrode film 104 are formed.
Subsequently, as explained with reference to FIG. 10B, ions of boron (B) are implanted into the semiconductor substrate 101 through the gate oxide film 103 and the gate electrode film 104 to form a channel region 105 which has the impurity concentration peak in the interior of the substrate 101.
Finally, as explained with reference to FIG. 10C, the gate electrode film 104 is patterned to form a gate electrode 104. Then, using the gate electrode 104 as a mask, ions of arsenic (As) are implanted into the semiconductor substrate 101 to form the source 106 and the drain 107, so that the MIS transistor having the retrograde channel structure is formed.
In this method, the channel region 105 is formed by ion implantation after the gate oxide film 103 is formed. Therefore, it is possible to prevent that the implanted B impurity is thermally diffused by a high temperature treatment performed to form the gate oxide film 103. However, since ion implantation is performed through the gate oxide film 103 and the gate electrode 104, acceleration energy has to be increased, resulting in a broad profile after the implantation. Therefore, this method is not suitable for forming a miniaturized transistor.
Compared to this, Patent Document (Japanese Laid-Open Patent Publication No. 2002-368212) discloses a retrograde channel region formation method including the steps of: implanting ions of indium (In) having a greater mass and B having a higher activation rate into the semiconductor substrate at the same depth; and performing a short-time thermal treatment for about 10 seconds at a temperature of 950° C.
According to this method, the short-time thermal treatment performed after ions are implanted redistributes B as steeply as a distribution of In. This makes it possible to form a channel region which has a depth profile of In but in which B electrically serves as an impurity. Therefore, it is possible to form a retrograde channel region having a steep distribution.